1. Field of the Invention
The present invention relates to a parallel multiplication circuit, and more specifically to a high speed multiplication circuit using a second-order Booth's decode algorithm.
2. Description of related art
In the prior art, this type of parallel multiplication circuits have been constructed to use a Booth's decode circuit so as to generate three control signals from data of three continuous bits of an inputted multiplier. The three control signals are indicative of (1) whether the data is single or double, (2) whether the data is positive or negative, and (3) whether or not the data is zero (0), respectively.
For example, one typical Booth's decoder incorporated in the conventional parallel multiplication circuit has been constituted to include a first exclusive-NOR gate having a pair of inputs connected to receive a first input "a" and a third input "c", respectively and an output for generating a first output ".alpha.", a second exclusive-NOR gate having a pair of inputs connected to receive a second input "b" and the third input "c", respectively, an OR gate having a pair of inputs connected to the outputs of the first and second exclusive-NOR gates, respectively, a NAND gate having a pair of inputs connected to an output of the OR gate and the third input "c", respectively and an output for generating a second output ".beta.", and an inverter having an input connected to the output of the OR gate and an output for generating a third output ".gamma.".
Here, assuming that three bits of data of a multiplier inputted to the Booth's decode circuit are called "a", "b" and "c" in the order from its least significant bit towards its most significant bit, a control signal .alpha. indicating that the data is double is generated by a logical equation expressed as follows: EQU .alpha.=(a.sym.c).multidot.(b.sym.c)
Similarly, a control signal .beta. indicating that the data is positive is generated by a logical equation expressed as follows: EQU .beta.={(a.sym.c)+(b.sym.c)}.multidot.c
In addition, a control signal .gamma. indicating that the data is zero (0) is generated by a logical equation expressed as follows: EQU .gamma.=(a.sym.c)+(b.sym.c)
The following TABLE I shows the truth values of the above mentioned logical equations.
TABLE I ______________________________________ a b c Actual Value .alpha. .beta. .gamma. ______________________________________ 0 0 0 0 0 1 1 1 0 0 1 0 1 0 0 1 0 1 0 1 0 1 1 0 2 1 1 0 0 0 1 -2 1 0 0 1 0 1 -1 0 0 0 0 1 1 -1 0 0 0 1 1 1 0 0 1 1 ______________________________________
For example, assuming that "1, 0, 1" is inputted to the inputs "a", "b" and "c" of the above mentioned Booth's decoder, an actual value is "-1", and "0, 0, 0" is outputted from the outputs ".alpha.", ".beta." and ".gamma.".
By using the above mentioned Booth's decoder and a partial product generation circuit, the conventional parallel multiplication circuits have been constructed.
However, the parallel multiplication circuits using the above mentioned Booth's decoder have been complicated in construction and large in circuit scale, because the Booth's decoder is configured to generate the output signals accurately indicating that (1) whether the data is single or double, (2) whether the data is positive or negative, and (3) whether or not the data is zero (0), respectively. In addition, the number of required series-connected gate stages is large in the conventional parallel multiplication circuits, and therefore, the operation speed of the multiplication circuits is low.